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PRELIMINARY
CYM1836V33
128K x 32 3.3V Static RAM Module
Features
* High-density 3.3V 4-megabit SRAM module * 32-bit standard footprint supports densities from 16K x 32 through 1M x 32 * High-speed CMOS SRAMs * Access time of 25 ns -- Low active power 1.6W (max.) at 20 ns * 2.0V Data Retention (ICCDRL = 0.8 mA, max.) * SMD technology * TTL-compatible inputs and outputs * Available in 64-pin SIMM, 64-pin ZIP format or 72-pin SIMM format. lects (CS1, CS2, CS3, CS4) are used to independently enable the four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. Writing to each byte is accomplished when the appropriate chip select (CS) and write enable (WE) inputs are both LOW. Data on the input/output pins (I/O) is written into the memory location specified on the address pins (A0 through A 16). Reading the device is accomplished by taking the chip select (CS) LOW while write enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the data input/output pins (I/O). The data input/output pins stay at the high-impedance state when write enable is LOW or the appropriate chip selects are HIGH. Two pins (PD0 and PD 1) are used to identify module memory density in applications where alternate versions of the JEDEC-standard modules can be interchanged. 72-pin SIMM Top View
NC PD3 PD0 I/O0 I/O1 I/O2 I/O3 VCC A7 A8 A9 I/O4 I/O5 I/O6 I/O7 WE A14 CS1 CS3 A16 GND I/O16 I/O17 I/O18 I/O19 A10 A11 A12 A13 I/O20 I/O21 I/O22 I/O23 GND NC NC
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
Functional Description
The CYM1836V33 is a 3.3V high-performance 4-megabit static RAM module organized as 128K words by 32 bits. This module is constructed from four 128K x 8 SRAMs in SOJ packages mounted on an epoxy laminate board with pins. Four chip se-
Logic Block Diagram
Pin Configurations
64-pin ZIP/SIMM Top View
PD0-OPEN PD1-OPEN
PD0 I/O0 I/O1 I/O2 I/O3 VCC A7 A8 A9 I/O4 I/O5 I/O6 I/O7 WE A14 CS1 CS3 A16 GND I/O16 I/O17 I/O18 I/O19 A10 A11 A12 A13 I/O20 I/O21 I/O22 I/O23 GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 GND PD1 I/O8 I/O9 I/O10 I/O11 A0 A1 A2 I/O12 I/O13 I/O14 I/O15 GND A15 CS2 CS4 NC OE I/O24 I/O25 I/O26 I/O27 A3 A4 A5 VCC A6 I/O28 I/O29 I/O30 I/O31 1836V33-2
A0- A16 OE WE
17
PD0 PD1 PD2 PD3 -
OPEN OPEN OPEN GND
128K x 8 SRAM CS1 128K x 8 SRAM CS2 128K x 8 SRAM CS3 128K x 8 SRAM CS4
4
I/O0 -I/O7
4
I/O8 -I/O15
NC PD2 GND PD1 I/O8 I/O9 I/O10 I/O11 A0 A1 A2 I/O12 I/O13 I/O14 I/O15 GND A15 CS2 CS4 NC OE I/O24 I/O25 I/O26 I/O27 A3 A4 A5 VCC A6 I/O28 I/O29 I/O30 I/O31 A18 NC
4
I/O16 -I/O23
4
I/O24 -I/O31
1836V33-1
1836V33-3
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 April 29, 1998
PRELIMINARY
Selection Guide
1836V33-15 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA)
Shaded area contains advance information.
CYM1836V33
1836V33-20 20 480 20
1836V33-25 1836V33-30 1836V33-35 1836V33-45 25 440 20 30 440 20 35 440 20 45 440 20
15 520 20
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -55C to +125C Ambient Temperature with Power Applied ............................................... -10C to +85C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State .....................................-0.5V to +VCC + 0.5V DC Input Voltage..................................-0.5V to +VCC + 0.5V
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC 3.3V 300mV
Electrical Characteristics Over the Operating Range
1836V33-15 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CS Power-Down Current[1] Automatic CS Power-Down Current[1] GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., IOUT = 0 mA, CS < VIL VCC = Max., CS > VIH, Min. Duty Cycle = 100% VCC = Max., CS > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.3 -4 -5 Min. 2.4 0.4 VCC +0.3 0.8 +4 +5 520 100 20 2.2 -0.3 -4 -5 Max. 1836V33-20, 25, 30, 35, 45 Min. 2.4 0.4 VCC +0.3 0.8 +4 +5 480 (20ns) 440 80 20 Max. Unit V V V V A A mA mA mA
Shaded area contains advance information.
Capacitance[2]
Parameter CIN COUT Description Input Capacitance
[3]
Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V
Max. 24 8
Unit pF pF
Output Capacitance
Notes: 1. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 2. Tested on a sample basis. 3. 20 pF on CS, 40 pF all others.
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PRELIMINARY
AC Test Loads and Waveforms
R1 481 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 255 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 255 R1 481 3.0V 90% GND < 5 ns
1836V33-4
CYM1836V33
ALL INPUT PULSES 90% 10% < 5 ns
1836V33-5
10%
(a)
(b)
Equivalent to: OUTPUT
THE VENIN EQUIVALENT 167 1.73V
Switching Characteristics Over the Operating Range[4]
1836V33-15 1836V33-20 1836V33-25 1836V33-30 1836V33-35 1836V33-45 Parameter READ CYCLE tRC tAA tOHA Read Cycle Time Address to Data Valid Output Hold from Address Change CS LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CS LOW to Low Z[5] CS HIGH to High Z[5, 6] 3 7 0 7 3 10 3 15 15 3 20 20 3 25 25 3 30 30 3 35 35 3 45 45 ns ns ns Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tACS tDOE tLZOE tHZOE tLZCS tHZCS
15 7 0
20 8 0 8 3
25 8 0 10 3 10
30 10 0 11 3 13
35 12 0 12 3 15
45 15
ns ns ns
15
ns ns
18
ns
Shaded area contains advance information. Notes: 4. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed by design and not 100% tested. 6. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured 500 mV from steady-state voltage.
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PRELIMINARY
Switching Characteristics Over the Operating Range[4] (continued)
CYM1836V33
1836V33-15 1836V33-20 1836V33-25 1836V33-30 1836V33-35 1836V33-45 Parameter tWC tSCS tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Description Write Cycle Time CS LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z[6] Min. 15 12 12 0 0 12 7 0 3 0 7 Max. Min. 20 15 15 0 0 15 10 0 3 0 8 Max. Min. 25 15 15 0 0 15 10 0 3 0 10 Max. Min. 30 18 18 0 0 18 13 0 3 0 15 Max. Min. 35 20 20 0 0 20 15 0 3 0 15 Max. Min. 45 25 25 0 0 25 20 0 3 0 18 Max. Unit ns ns ns ns ns ns ns ns ns ns WRITE CYCLE[7]
Shaded area contains advance information.
Switching Waveforms
Read Cycle No.1[8, 9]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
1836V33-6
Read Cycle No. 2[8, 10]
CS tACS OE tDOE tLZOE HIGH IMPEDANCE DATA OUT tLZCS DATA VALID
1836V33-7
tRC
tHZOE tHZCS
HIGH IMPEDANCE
Notes: 7. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 8. WE is HIGH for read cycle. 9. Device is continuously selected, CS = VIL and OE= VIL. 10. Address valid prior to or coincident with CS transition LOW.
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PRELIMINARY
Switching Waveforms (continued)
Write Cycle No.1 (WE Controlled)[7]
tWC ADDRESS tSCS CS tSA WE tSD DATA IN DATA VALID tHZWE DATA OUT DATA UNDEFINED tLZWE HIGH IMPEDANCE tHD tAW tPWE tHA
CYM1836V33
1836V33-8
Write Cycle No. 2 (CS Controlled)[7, 11]
tWC ADDRESS tSA CS tAW tPWE WE tSD DATA IN DATA VALID tHZWE DATA OUT HIGH IMPEDANCE DATA UNDEFINED
1836V33-9
tSCS
tHA
tHD
Note: 11. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Truth Table
CSN H L L L WE X H L H OE X L X H Input/Outputs High Z Data Out Data In High Z Read Write Deselect Mode Deselect/Power-Down
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PRELIMINARY
Ordering Information[12]
Speed (ns) 15 20 25 Ordering Code CYM1836V33PM-15C CYM1836V33PZ-15C CYM1836V33PM-20C CYM1836V33PZ-20C CYM1836V33PM-25C CYM1836V33PZ-25C CYM1836V33P8-25C 30 CYM1836V33PM-30C CYM1836V33PZ-30C CYM1836V33P8-25C 35 CYM1836V33PM-35C CYM1836V33PZ-35C CYM1836V33P8-25C 45 CYM1836V33PM-45C CYM1836V33PZ-45C CYM1836V33P8-25C
Shaded area contains advance information. Note: 12. 64-pin SIMM suitable for use in angled SIMM applications.
CYM1836V33
Package Name PM03 PZ08 PM03 PZ08 PM03 PZ08 PM04 PM03 PZ08 PM04 PM03 PZ08 PM04 PM03 PZ08 PM04
Package Type 64-Pin SIMM Module 72-Pin SIMM Module (Gold Contacts) 64-Pin SIMM Module 72-Pin SIMM Module (Gold Contacts) 64-Pin SIMM Module 72-Pin SIMM Module (Gold Contacts) 72-Pin ZIP Module (Gold Contacts) 64-Pin SIMM Module 72-Pin SIMM Module (Gold Contacts) 72-Pin ZIP Module (Gold Contacts) 64-Pin SIMM Module 72-Pin SIMM Module (Gold Contacts) 72-Pin ZIP Module (Gold Contacts) 64-Pin SIMM Module 72-Pin SIMM Module (Gold Contacts) 72-Pin ZIP Module (Gold Contacts)
Operating Range Commercial Commercial Commercial
Commercial
Commercial
Commercial
Document #: 38-M-00085
Package Diagrams
64-Pin SIMM Module PM03
3.855 MAX. 3.580/3.588 124/.126 DIA. 2 PLCS 128KX8 .397/.403 .245/.255 .135 REF. 128KX8 128KX8 128KX8 .595 MAX. . 200 MAX.
PIN 1 .075/.085
.061/.063 R .249/.251
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PRELIMINARY
Package Diagrams (continued)
64-Pin ZIP Module PZ08
CYM1836V33
72-Pin Plastic SIMM Module PM04
(c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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